IDXD specification definitions. More...

Data Structures
struct	idxd_hw_desc

struct	dsa_hw_comp_record

struct	iaa_hw_comp_record

struct	iaa_aecs

union	idxd_gencap_register

union	idxd_wqcap_register

union	idxd_groupcap_register

union	idxd_enginecap_register

struct	idxd_opcap_register

union	idxd_offsets_register

union	idxd_gencfg_register

union	idxd_genctrl_register

union	idxd_gensts_register

union	idxd_intcause_register

union	idxd_cmd_register

union	idxd_cmdsts_register

union	idxd_cmdcap_register

union	idxd_swerr_register

struct	idxd_registers

union	idxd_group_flags

struct	idxd_grpcfg

struct	idxd_grptbl

union	idxd_wqcfg

Macros
#define	IDXD_MMIO_BAR 0

#define	IDXD_WQ_BAR 2

#define	PORTAL_SIZE 0x1000

#define	WQ_TOTAL_PORTAL_SIZE (PORTAL_SIZE * 4)

#define	PORTAL_STRIDE 0x40

#define	PORTAL_MASK (PORTAL_SIZE - 1)

#define	WQCFG_SHIFT 5

#define	IDXD_TABLE_OFFSET_MULT 0x100

#define	IDXD_CLEAR_CRC_FLAGS 0xFFFFu

#define	IDXD_FLAG_FENCE (1 << 0)

#define	IDXD_FLAG_COMPLETION_ADDR_VALID (1 << 2)

#define	IDXD_FLAG_REQUEST_COMPLETION (1 << 3)

#define	IDXD_FLAG_CACHE_CONTROL (1 << 8)

#define	IDXD_FLAG_DEST_READBACK (1 << 14)

#define	IDXD_FLAG_DEST_STEERING_TAG (1 << 15)

#define	IDXD_FLAG_CRC_READ_CRC_SEED (1 << 16)

#define	IDXD_DSA_STATUS_DIF_ERROR 0x9

#define	IDXD_DIF_FLAG_INVERT_CRC_RESULT (1 << 3)

#define	IDXD_DIF_FLAG_INVERT_CRC_SEED (1 << 2)

#define	IDXD_DIF_FLAG_DIF_BLOCK_SIZE_512 0x0

#define	IDXD_DIF_FLAG_DIF_BLOCK_SIZE_520 0x1

#define	IDXD_DIF_FLAG_DIF_BLOCK_SIZE_4096 0x2

#define	IDXD_DIF_FLAG_DIF_BLOCK_SIZE_4104 0x3

#define	IDXD_DIF_SOURCE_FLAG_SOURCE_REF_TAG_TYPE (1 << 7)

#define	IDXD_DIF_SOURCE_FLAG_REF_TAG_CHECK_DISABLE (1 << 6)

#define	IDXD_DIF_SOURCE_FLAG_GUARD_CHECK_DISABLE (1 << 5)

#define	IDXD_DIF_SOURCE_FLAG_SOURCE_APP_TAG_TYPE (1 << 4)

#define	IDXD_DIF_SOURCE_FLAG_APP_AND_REF_TAG_F_DETECT (1 << 3)

#define	IDXD_DIF_SOURCE_FLAG_APP_TAG_F_DETECT (1 << 2)

#define	IDXD_DIF_SOURCE_FLAG_ALL_F_DETECT (1 << 1)

#define	IDXD_DIF_SOURCE_FLAG_ENABLE_ALL_F_DETECT_ERR (1)

#define	IAA_FLAG_RD_SRC2_AECS (1 << 16)

#define	IAA_COMP_FLUSH_OUTPUT (1 << 1)

#define	IAA_COMP_APPEND_EOB (1 << 2)

#define	IAA_COMP_FLAGS (IAA_COMP_FLUSH_OUTPUT \| IAA_COMP_APPEND_EOB)

#define	IAA_DECOMP_ENABLE (1 << 0)

#define	IAA_DECOMP_FLUSH_OUTPUT (1 << 1)

#define	IAA_DECOMP_CHECK_FOR_EOB (1 << 2)

#define	IAA_DECOMP_STOP_ON_EOB (1 << 3)

#define	IAA_DECOMP_FLAGS

Enumerations
enum	dsa_completion_status { DSA_COMP_NONE = 0 , DSA_COMP_SUCCESS = 1 , DSA_COMP_SUCCESS_PRED = 2 , DSA_COMP_PAGE_FAULT_NOBOF = 3 , DSA_COMP_PAGE_FAULT_IR = 4 , DSA_COMP_BATCH_FAIL = 5 , DSA_COMP_BATCH_PAGE_FAULT = 6 , DSA_COMP_DR_OFFSET_NOINC = 7 , DSA_COMP_DR_OFFSET_ERANGE = 8 , DSA_COMP_DIF_ERR = 9 , DSA_COMP_BAD_OPCODE = 16 , DSA_COMP_INVALID_FLAGS = 17 , DSA_COMP_NOZERO_RESERVE = 18 , DSA_COMP_XFER_ERANGE = 19 , DSA_COMP_DESC_CNT_ERANGE = 20 , DSA_COMP_DR_ERANGE = 21 , DSA_COMP_OVERLAP_BUFFERS = 22 , DSA_COMP_DCAST_ERR = 23 , DSA_COMP_DESCLIST_ALIGN = 24 , DSA_COMP_INT_HANDLE_INVAL = 25 , DSA_COMP_CRA_XLAT = 26 , DSA_COMP_CRA_ALIGN = 27 , DSA_COMP_ADDR_ALIGN = 28 , DSA_COMP_PRIV_BAD = 29 , DSA_COMP_TRAFFIC_CLASS_CONF = 30 , DSA_COMP_PFAULT_RDBA = 31 , DSA_COMP_HW_ERR1 = 32 , DSA_COMP_HW_ERR_DRB = 33 , DSA_COMP_TRANSLATION_FAIL = 34 }

enum	iaa_completion_status { IAA_COMP_NONE = 0 , IAA_COMP_SUCCESS = 1 , IAA_COMP_PAGE_FAULT_IR = 4 , IAA_COMP_OUTBUF_OVERFLOW = 5 , IAA_COMP_BAD_OPCODE = 16 , IAA_COMP_INVALID_FLAGS = 17 , IAA_COMP_NOZERO_RESERVE = 18 , IAA_COMP_INVALID_SIZE = 19 , IAA_COMP_OVERLAP_BUFFERS = 22 , IAA_COMP_INT_HANDLE_INVAL = 25 , IAA_COMP_CRA_XLAT = 32 , IAA_COMP_CRA_ALIGN = 33 , IAA_COMP_ADDR_ALIGN = 34 , IAA_COMP_PRIV_BAD = 35 , IAA_COMP_TRAFFIC_CLASS_CONF = 36 , IAA_COMP_PFAULT_RDBA = 37 , IAA_COMP_HW_ERR1 = 38 , IAA_COMP_TRANSLATION_FAIL = 39 , IAA_COMP_PRS_TIMEOUT = 40 , IAA_COMP_WATCHDOG = 41 , IAA_COMP_INVALID_COMP_FLAG = 48 , IAA_COMP_INVALID_FILTER_FLAG = 49 , IAA_COMP_INVALID_NUM_ELEMS = 50 }

enum	idxd_wq_state { WQ_DISABLED = 0 , WQ_ENABLED = 1 }

enum	idxd_wq_flag { WQ_FLAG_DEDICATED = 0 , WQ_FLAG_BOF = 1 }

enum	idxd_wq_type { WQT_NONE = 0 , WQT_KERNEL = 1 , WQT_USER = 2 , WQT_MDEV = 3 }

enum	idxd_dev_state { IDXD_DEVICE_STATE_DISABLED = 0 , IDXD_DEVICE_STATE_ENABLED = 1 , IDXD_DEVICE_STATE_DRAIN = 2 , IDXD_DEVICE_STATE_HALT = 3 }

enum	idxd_device_reset_type { IDXD_DEVICE_RESET_SOFTWARE = 0 , IDXD_DEVICE_RESET_FLR = 1 , IDXD_DEVICE_RESET_WARM = 2 , IDXD_DEVICE_RESET_COLD = 3 }

enum	idxd_cmds { IDXD_ENABLE_DEV = 1 , IDXD_DISABLE_DEV = 2 , IDXD_DRAIN_ALL = 3 , IDXD_ABORT_ALL = 4 , IDXD_RESET_DEVICE = 5 , IDXD_ENABLE_WQ = 6 , IDXD_DISABLE_WQ = 7 , IDXD_DRAIN_WQ = 8 , IDXD_ABORT_WQ = 9 , IDXD_RESET_WQ = 10 }

enum	idxd_cmdsts_err { IDXD_CMDSTS_SUCCESS = 0 , IDXD_CMDSTS_INVAL_CMD = 1 , IDXD_CMDSTS_INVAL_WQIDX = 2 , IDXD_CMDSTS_HW_ERR = 3 , IDXD_CMDSTS_ERR_DEV_ENABLED = 16 , IDXD_CMDSTS_ERR_CONFIG = 17 , IDXD_CMDSTS_ERR_BUSMASTER_EN = 18 , IDXD_CMDSTS_ERR_PASID_INVAL = 19 , IDXD_CMDSTS_ERR_WQ_SIZE_ERANGE = 20 , IDXD_CMDSTS_ERR_GRP_CONFIG = 21 , IDXD_CMDSTS_ERR_GRP_CONFIG2 = 22 , IDXD_CMDSTS_ERR_GRP_CONFIG3 = 23 , IDXD_CMDSTS_ERR_GRP_CONFIG4 = 24 , IDXD_CMDSTS_ERR_DEV_NOTEN = 32 , IDXD_CMDSTS_ERR_WQ_ENABLED = 33 , IDXD_CMDSTS_ERR_WQ_SIZE = 34 , IDXD_CMDSTS_ERR_WQ_PRIOR = 35 , IDXD_CMDSTS_ERR_WQ_MODE = 36 , IDXD_CMDSTS_ERR_BOF_EN = 37 , IDXD_CMDSTS_ERR_PASID_EN = 38 , IDXD_CMDSTS_ERR_MAX_BATCH_SIZE = 39 , IDXD_CMDSTS_ERR_MAX_XFER_SIZE = 40 , IDXD_CMDSTS_ERR_DIS_DEV_EN = 49 , IDXD_CMDSTS_ERR_DEV_NOT_EN = 50 , IDXD_CMDSTS_ERR_INVAL_INT_IDX = 65 , IDXD_CMDSTS_ERR_NO_HANDLE = 66 }

enum	idxd_wq_hw_state { IDXD_WQ_DEV_DISABLED = 0 , IDXD_WQ_DEV_ENABLED = 1 , IDXD_WQ_DEV_BUSY = 2 }

Functions
struct idxd_hw_desc	__attribute ((aligned(64)))

	SPDK_STATIC_ASSERT (sizeof(struct idxd_hw_desc)==64, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(struct dsa_hw_comp_record)==32, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(struct iaa_hw_comp_record)==64, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(struct iaa_aecs)==1568, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_gencap_register)==8, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_wqcap_register)==8, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_groupcap_register)==8, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_enginecap_register)==8, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(struct idxd_opcap_register)==32, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_offsets_register)==16, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_gencfg_register)==4, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_genctrl_register)==4, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_gensts_register)==4, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_intcause_register)==4, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_cmd_register)==4, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_cmdsts_register)==4, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_cmdcap_register)==4, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_swerr_register)==32, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(struct idxd_registers)==0xE0, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_group_flags)==4, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(struct idxd_grpcfg)==64, "size mismatch")

	SPDK_STATIC_ASSERT (sizeof(union idxd_wqcfg)==32, "size mismatch")

Variables
uint32_t	pasid

uint32_t	rsvd

uint32_t	priv

uint32_t	flags

uint32_t	opcode

uint64_t	completion_addr

union {

uint64_t src_addr

uint64_t src1_addr

uint64_t readback_addr

uint64_t pattern

uint64_t desc_list_addr

};

union {

uint64_t dst_addr

uint64_t readback_addr2

uint64_t src2_addr

uint64_t comp_pattern

};

union {

uint32_t src1_size

uint32_t xfer_size

uint32_t desc_count

};

uint16_t	int_handle

union {

uint16_t rsvd1

uint16_t compr_flags

uint16_t decompr_flags

};

union {

struct {

uint64_t src2_addr

uint32_t max_dst_size

uint32_t src2_size

uint32_t filter_flags

uint32_t num_inputs

} iaa

uint8_t expected_res

struct {

uint64_t addr

uint32_t max_size

} delta

uint32_t delta_rec_size

uint64_t dest2

struct {

uint32_t seed

uint32_t rsvd

uint64_t addr

} crc32c

struct {

uint8_t src_flags

uint8_t rsvd1

uint8_t flags

uint8_t rsvd2 [5]

uint32_t ref_tag_seed

uint16_t app_tag_mask

uint16_t app_tag_seed

} dif_chk

struct {

uint8_t rsvd1

uint8_t dest_flag

uint8_t flags

uint8_t rsvd2 [13]

uint32_t ref_tag_seed

uint16_t app_tag_mask

uint16_t app_tag_seed

} dif_ins

struct {

uint8_t src_flags

uint8_t dest_flags

uint8_t flags

uint8_t rsvd [5]

uint32_t src_ref_tag_seed

uint16_t src_app_tag_mask

uint16_t src_app_tag_seed

uint32_t dest_ref_tag_seed

uint16_t dest_app_tag_mask

uint16_t dest_app_tag_seed

} dif_upd

struct {

uint8_t src_flags

uint8_t rsvd1

uint8_t flags

uint8_t rsvd2 [5]

uint32_t ref_tag_seed

uint16_t app_tag_mask

uint16_t app_tag_seed

} dif_strip

uint8_t op_specific [24]

};

struct dsa_hw_comp_record	__attribute

Detailed Description

IDXD specification definitions.

Macro Definition Documentation

◆ IAA_DECOMP_FLAGS

#define IAA_DECOMP_FLAGS

Value:

                                        (IAA_DECOMP_ENABLE | \
                                        IAA_DECOMP_FLUSH_OUTPUT | \
                                        IAA_DECOMP_CHECK_FOR_EOB | \
                                        IAA_DECOMP_STOP_ON_EOB)

idxd_spec.h File Reference

Data Structures

Macros

Enumerations

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ IAA_DECOMP_FLAGS