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enum | dsa_completion_status {
DSA_COMP_NONE = 0
, DSA_COMP_SUCCESS = 1
, DSA_COMP_SUCCESS_PRED = 2
, DSA_COMP_PAGE_FAULT_NOBOF = 3
,
DSA_COMP_PAGE_FAULT_IR = 4
, DSA_COMP_BATCH_FAIL = 5
, DSA_COMP_BATCH_PAGE_FAULT = 6
, DSA_COMP_DR_OFFSET_NOINC = 7
,
DSA_COMP_DR_OFFSET_ERANGE = 8
, DSA_COMP_DIF_ERR = 9
, DSA_COMP_BAD_OPCODE = 16
, DSA_COMP_INVALID_FLAGS = 17
,
DSA_COMP_NOZERO_RESERVE = 18
, DSA_COMP_XFER_ERANGE = 19
, DSA_COMP_DESC_CNT_ERANGE = 20
, DSA_COMP_DR_ERANGE = 21
,
DSA_COMP_OVERLAP_BUFFERS = 22
, DSA_COMP_DCAST_ERR = 23
, DSA_COMP_DESCLIST_ALIGN = 24
, DSA_COMP_INT_HANDLE_INVAL = 25
,
DSA_COMP_CRA_XLAT = 26
, DSA_COMP_CRA_ALIGN = 27
, DSA_COMP_ADDR_ALIGN = 28
, DSA_COMP_PRIV_BAD = 29
,
DSA_COMP_TRAFFIC_CLASS_CONF = 30
, DSA_COMP_PFAULT_RDBA = 31
, DSA_COMP_HW_ERR1 = 32
, DSA_COMP_HW_ERR_DRB = 33
,
DSA_COMP_TRANSLATION_FAIL = 34
} |
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enum | iaa_completion_status {
IAA_COMP_NONE = 0
, IAA_COMP_SUCCESS = 1
, IAA_COMP_PAGE_FAULT_IR = 4
, IAA_COMP_OUTBUF_OVERFLOW = 5
,
IAA_COMP_BAD_OPCODE = 16
, IAA_COMP_INVALID_FLAGS = 17
, IAA_COMP_NOZERO_RESERVE = 18
, IAA_COMP_INVALID_SIZE = 19
,
IAA_COMP_OVERLAP_BUFFERS = 22
, IAA_COMP_INT_HANDLE_INVAL = 25
, IAA_COMP_CRA_XLAT = 32
, IAA_COMP_CRA_ALIGN = 33
,
IAA_COMP_ADDR_ALIGN = 34
, IAA_COMP_PRIV_BAD = 35
, IAA_COMP_TRAFFIC_CLASS_CONF = 36
, IAA_COMP_PFAULT_RDBA = 37
,
IAA_COMP_HW_ERR1 = 38
, IAA_COMP_TRANSLATION_FAIL = 39
, IAA_COMP_PRS_TIMEOUT = 40
, IAA_COMP_WATCHDOG = 41
,
IAA_COMP_INVALID_COMP_FLAG = 48
, IAA_COMP_INVALID_FILTER_FLAG = 49
, IAA_COMP_INVALID_NUM_ELEMS = 50
} |
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enum | idxd_wq_state { WQ_DISABLED = 0
, WQ_ENABLED = 1
} |
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enum | idxd_wq_flag { WQ_FLAG_DEDICATED = 0
, WQ_FLAG_BOF = 1
} |
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enum | idxd_wq_type { WQT_NONE = 0
, WQT_KERNEL = 1
, WQT_USER = 2
, WQT_MDEV = 3
} |
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enum | idxd_dev_state { IDXD_DEVICE_STATE_DISABLED = 0
, IDXD_DEVICE_STATE_ENABLED = 1
, IDXD_DEVICE_STATE_DRAIN = 2
, IDXD_DEVICE_STATE_HALT = 3
} |
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enum | idxd_device_reset_type { IDXD_DEVICE_RESET_SOFTWARE = 0
, IDXD_DEVICE_RESET_FLR = 1
, IDXD_DEVICE_RESET_WARM = 2
, IDXD_DEVICE_RESET_COLD = 3
} |
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enum | idxd_cmds {
IDXD_ENABLE_DEV = 1
, IDXD_DISABLE_DEV = 2
, IDXD_DRAIN_ALL = 3
, IDXD_ABORT_ALL = 4
,
IDXD_RESET_DEVICE = 5
, IDXD_ENABLE_WQ = 6
, IDXD_DISABLE_WQ = 7
, IDXD_DRAIN_WQ = 8
,
IDXD_ABORT_WQ = 9
, IDXD_RESET_WQ = 10
} |
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enum | idxd_cmdsts_err {
IDXD_CMDSTS_SUCCESS = 0
, IDXD_CMDSTS_INVAL_CMD = 1
, IDXD_CMDSTS_INVAL_WQIDX = 2
, IDXD_CMDSTS_HW_ERR = 3
,
IDXD_CMDSTS_ERR_DEV_ENABLED = 16
, IDXD_CMDSTS_ERR_CONFIG = 17
, IDXD_CMDSTS_ERR_BUSMASTER_EN = 18
, IDXD_CMDSTS_ERR_PASID_INVAL = 19
,
IDXD_CMDSTS_ERR_WQ_SIZE_ERANGE = 20
, IDXD_CMDSTS_ERR_GRP_CONFIG = 21
, IDXD_CMDSTS_ERR_GRP_CONFIG2 = 22
, IDXD_CMDSTS_ERR_GRP_CONFIG3 = 23
,
IDXD_CMDSTS_ERR_GRP_CONFIG4 = 24
, IDXD_CMDSTS_ERR_DEV_NOTEN = 32
, IDXD_CMDSTS_ERR_WQ_ENABLED = 33
, IDXD_CMDSTS_ERR_WQ_SIZE = 34
,
IDXD_CMDSTS_ERR_WQ_PRIOR = 35
, IDXD_CMDSTS_ERR_WQ_MODE = 36
, IDXD_CMDSTS_ERR_BOF_EN = 37
, IDXD_CMDSTS_ERR_PASID_EN = 38
,
IDXD_CMDSTS_ERR_MAX_BATCH_SIZE = 39
, IDXD_CMDSTS_ERR_MAX_XFER_SIZE = 40
, IDXD_CMDSTS_ERR_DIS_DEV_EN = 49
, IDXD_CMDSTS_ERR_DEV_NOT_EN = 50
,
IDXD_CMDSTS_ERR_INVAL_INT_IDX = 65
, IDXD_CMDSTS_ERR_NO_HANDLE = 66
} |
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enum | idxd_wq_hw_state { IDXD_WQ_DEV_DISABLED = 0
, IDXD_WQ_DEV_ENABLED = 1
, IDXD_WQ_DEV_BUSY = 2
} |
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