AMD NTB specification / on-the-wire protocol definitions. More...

Macros
#define	BIT(n) (1UL << (n))

#define	NTB_SPAD_USER "spad_user_"

#define	NTB_SPAD_USER_LEN (sizeof(NTB_SPAD_USER) - 1)

#define	NTB_SPAD_USER_MAX_NUM 4

#define	NTB_ATTR_NAME_LEN 30

#define	NTB_PCIE_BAR 0

#define	NTB_MAX_HW_QUEUES 16

#define	AMD_DB_COUNT 16

#define	AMD_MSIX_VECTOR_COUNT 24

#define	AMD_SPADS_COUNT 16

#define	AMD_MW_COUNT 2

#define	AMD_MW_IDX 2

#define	AMD_PEER_OFFSET 0x400

#define	AMD_SIDEINFO_OFFSET 0x408

#define	AMD_DBFM_OFFSET 0x450

#define	AMD_DBREQ_OFFSET 0x454

#define	AMD_DBMASK_OFFSET 0x45C

#define	AMD_DBSTAT_OFFSET 0x460

#define	AMD_INTMASK_OFFSET 0x470

#define	AMD_INTSTAT_OFFSET 0x474

#define	AMD_PMESTAT_OFFSET 0x480

#define	AMD_PEER_FLUSH_EVENT BIT(0)

#define	AMD_PEER_RESET_EVENT BIT(1)

#define	AMD_PEER_D3_EVENT BIT(2)

#define	AMD_PEER_PMETO_EVENT BIT(3)

#define	AMD_PEER_D0_EVENT BIT(4)

#define	AMD_LINK_UP_EVENT BIT(5)

#define	AMD_LINK_DOWN_EVENT BIT(6)

#define	AMD_EVENT_INTMASK

#define	AMD_BAR23_XLAT_OFFSET 0x438

#define	AMD_BAR23_LIMIT_OFFSET 0x418

#define	AMD_BAR45_XLAT_OFFSET 0x440

#define	AMD_BAR45_LIMIT_OFFSET 0x420

#define	AMD_SIDE_MASK BIT(0)

#define	AMD_SIDE_READY BIT(1)

#define	AMD_SPAD_OFFSET 0x210

#define	AMD_CNTL_OFFSET 0x200

#define	PMM_REG_CTL BIT(21)

#define	SMM_REG_CTL BIT(20)

#define	AMD_SMUACK_OFFSET 0x4A0

#define	AMD_NTB_LNK_STA_ACTIVE_BIT 0x2000

#define	AMD_NTB_LNK_STA_SPEED_MASK 0x000f

#define	AMD_NTB_LNK_STA_WIDTH_MASK 0x03f0

#define	AMD_NTB_LNK_STA_ACTIVE(x) (!!((x) & AMD_NTB_LNK_STA_ACTIVE_BIT))

#define	AMD_NTB_LNK_STA_SPEED(x) ((x) & AMD_NTB_LNK_STA_SPEED_MASK)

#define	AMD_NTB_LNK_STA_WIDTH(x) (((x) & AMD_NTB_LNK_STA_WIDTH_MASK) >> 4)

Enumerations
enum	spdk_ntb_bar { NTB_BAR23 = 2 , NTB_BAR45 = 4 }

enum	spdk_ntb_topo { NTB_TOPO_NONE = 0 , NTB_TOPO_PRI , NTB_TOPO_SEC }
	NTB topology assignment, as exchanged over the link and returned by spdk_ntb_amd_attr_get(SPDK_NTB_TOPO_NAME). More...

enum	spdk_ntb_link { NTB_LINK_DOWN = 0 , NTB_LINK_UP }
	NTB link state, as returned by spdk_ntb_amd_attr_get(NTB_LINK_STATUS_NAME).

enum	spdk_ntb_spad_idx { SPAD_NUM_MWS = 1 }
	Layout of the peer-to-peer handshake scratchpad block. More...

Functions
	SPDK_STATIC_ASSERT ((AMD_DBSTAT_OFFSET &0x1)==0, "AMD_DBSTAT_OFFSET must be 2-byte aligned")

	SPDK_STATIC_ASSERT ((AMD_DBMASK_OFFSET &0x1)==0, "AMD_DBMASK_OFFSET must be 2-byte aligned")

	SPDK_STATIC_ASSERT ((AMD_DBREQ_OFFSET &0x1)==0, "AMD_DBREQ_OFFSET must be 2-byte aligned")

	SPDK_STATIC_ASSERT ((AMD_DBFM_OFFSET &0x1)==0, "AMD_DBFM_OFFSET must be 2-byte aligned")

	SPDK_STATIC_ASSERT ((AMD_SIDEINFO_OFFSET &0x3)==0, "AMD_SIDEINFO_OFFSET must be 4-byte aligned")

	SPDK_STATIC_ASSERT ((AMD_CNTL_OFFSET &0x3)==0, "AMD_CNTL_OFFSET must be 4-byte aligned")

	SPDK_STATIC_ASSERT ((AMD_INTMASK_OFFSET &0x3)==0, "AMD_INTMASK_OFFSET must be 4-byte aligned")

	SPDK_STATIC_ASSERT ((AMD_INTSTAT_OFFSET &0x3)==0, "AMD_INTSTAT_OFFSET must be 4-byte aligned")

	SPDK_STATIC_ASSERT ((AMD_PMESTAT_OFFSET &0x3)==0, "AMD_PMESTAT_OFFSET must be 4-byte aligned")

	SPDK_STATIC_ASSERT ((AMD_BAR23_XLAT_OFFSET &0x3)==0, "AMD_BAR23_XLAT_OFFSET must be 4-byte aligned")

	SPDK_STATIC_ASSERT ((AMD_BAR23_LIMIT_OFFSET &0x3)==0, "AMD_BAR23_LIMIT_OFFSET must be 4-byte aligned")

	SPDK_STATIC_ASSERT ((AMD_BAR45_XLAT_OFFSET &0x3)==0, "AMD_BAR45_XLAT_OFFSET must be 4-byte aligned")

	SPDK_STATIC_ASSERT ((AMD_BAR45_LIMIT_OFFSET &0x3)==0, "AMD_BAR45_LIMIT_OFFSET must be 4-byte aligned")

	SPDK_STATIC_ASSERT ((AMD_SPAD_OFFSET &0x3)==0, "AMD_SPAD_OFFSET must be 4-byte aligned")

Detailed Description

AMD NTB specification / on-the-wire protocol definitions.

This header is intentionally split out of include/spdk/ntb_amd.h so that consumers of the public driver API don't have to pull in the register layout, while applications that participate in the peer-to-peer scratchpad handshake (e.g. examples/ntb/perf) can.

Macro Definition Documentation

◆ AMD_EVENT_INTMASK

#define AMD_EVENT_INTMASK

Value:

                (AMD_PEER_FLUSH_EVENT | AMD_PEER_RESET_EVENT | \
                AMD_PEER_D3_EVENT | AMD_PEER_PMETO_EVENT | AMD_PEER_D0_EVENT | \
                AMD_LINK_UP_EVENT | AMD_LINK_DOWN_EVENT)

Enumeration Type Documentation

◆ spdk_ntb_spad_idx

enum spdk_ntb_spad_idx

Layout of the peer-to-peer handshake scratchpad block.

Both sides agree on these indices when publishing / consuming the memory-window configuration via the scratchpad registers. Index 0 is intentionally reserved (the AMD NTB hardware itself uses spad[0] for peer-discovery interlock).

Only the memory-window count is exchanged: the actual address translation is programmed directly into the peer's XLAT registers by ntb_amd_mw_set_trans(), so there is no need to publish per-window base addresses or sizes through the scratchpads.

◆ spdk_ntb_topo

enum spdk_ntb_topo

NTB topology assignment, as exchanged over the link and returned by spdk_ntb_amd_attr_get(SPDK_NTB_TOPO_NAME).

One side comes up as primary (PRI), the other as secondary (SEC); the AMD NTB exposes this through bit 0 of the side-info register and the driver caches it here.

Macros